1. Field of the Invention
The present invention relates to a semiconductor integrated circuit intended to reduce its power dissipation by controlling power supplies to an internal circuit in response to active and sleep periods of the internal circuit.
2. Description of the Prior Art
Recent developments in portable or mobile equipment have caused requirements of low power consumption semiconductor integrated circuits. For example, as shown in JP-A 7/212218, it has been proposed to provide a semiconductor integrated circuit with a power supply switch in which a power supply to an internal circuit is provided in an active period to operate the internal circuit, while the power supply to the internal circuit is stopped in a sleep period which don""t have to operate the internal circuit, e.g. in no operation by users. Particularly, by employing a MTCMOS (Multi-threshold CMOS) in which a threshold voltage of transistors constituting the power supply switch is larger than that of transistors constituting an internal circuit, the internal circuit which can operate by a low voltage power supply is achieved and leakage currents at the sleep period may be decreased.
As to the MTCMOS, a semiconductor further improved is described in JP-A 11/214962.
FIG. 11 illustrates a first semiconductor integrated circuit disclosed in JP-A 11/214962. The first semiconductor integrated circuit includes: a p-channel field effect transistor (hereinafter, referred to as pMOS transistor) QA1 as a power supply switch which is connected between a power supply line VDD and a virtual power supply line VA1; a n-channel field effect transistor (hereinafter, referred to as nMOS transistor) QB1 as a power supply switch which is connected between a power supply line GND and a virtual power supply line VB1; a diode D1 which is connected between the power supply line VDD and the virtual power supply line VA1; and a diode D2 which is connected between the power supply line GND and the virtual power supply line VB1. An internal circuit is connected between the virtual power supply lines VA1, VB1 which feed power supplies for operation. The internal circuit includes pMOS transistors Q3, Q4 and nMOS transistors Q5, Q6 each of which has an absolute value of the threshold voltage smaller than that of each of the transistors QA1, QB1.
The power supply line is applied with a voltage having a low voltage value LVDD around 1.0 V in an active period which operates the internal circuit and a voltage having a high voltage value HVDD of 3.3 V in a sleep period which does not use the internal circuit. The transistors QA1, QB1 are controlled by control signals CS1, CSB1 so as to be turned on simultaneously when the internal circuit is in the active period and turned off simultaneously when in the sleep period.
When the internal circuit is especially in the sleep period, each of the transistors Q3-Q6 is reversely biased to the source in a direction to increase the absolute value of the threshold voltage by the diodes D1, D2. When the internal circuit includes a sequential circuit such as a latch circuit, data latched in the sequential circuit in the active period may be latched without losses of the data in the sleep period, and a leakage current in the sleep period may be controlled.
FIG. 12 illustrates a second semiconductor integrated circuit disclosed in JP-A 11/214962. As only a part different from FIG. 11 is described, the second semiconductor integrated circuit includes: a pMOS transistor QA2, connected between a power supply line VDD1 and a backgate power supply line VA2, to be turned on/off simultaneously with a transistor QA1; and a pMOS transistor QA3, connected between a backgate power supply line VA2 and a power supply line VDD2, to be turned on/off complementarily with the transistor QA1. A diode D1 is connected between a virtual power supply line VA1 and the backgate power supply line VA2. A voltage having a voltage value LVDD is applied to the power supply line VDD1, while a voltage having a voltage value HVDD higher than the voltage value LVDD is applied to the power supply line VDD2. This second semiconductor integrated circuit also results in the above effect.
In the semiconductor integrated circuit as shown in FIG. 11, the virtual power supply line VA1 ideally becomes a potential level, which is equal to the power supply line VDD, in an active period of an internal circuit. However, in reality, a voltage drop is caused by a wiring resistance of the power supply line VDD, an ON-state resistance of the transistor QA1, and so on, and the voltage of the virtual power supply line VA1 becomes a value of (LVDDxe2x88x92xcex94VA1). On the other hand, the backgate potential of the transistors Q3, Q4 is LVDD. Since each backgate potential of the transistors Q3, Q4 is higher than the corresponding source potential, the operations of the transistors Q3, Q4 are made slower by an increase of the absolute values of the threshold voltages of these transistors Q3, Q4. In reality, the voltage of the virtual power supply line VB1 also becomes a value of xcex94VB1 higher than 0 V by a wiring resistance of the power supply line GND, an ON-state resistance of the transistor QB1, and soon. Since each backgate potential of the transistors Q5, Q6 is made lower than that of the corresponding source, the operations of the transistors Q5, Q6 are made slower by an increase of the absolute values of the threshold voltages of the transistors Q5, Q6. Thus, the operation speed of the internal circuit deteriorates.
On the other hand, in the semiconductor integrated circuit illustrated in FIG. 12, in an active period, as described above, the wiring resistance and the ON-state resistance of the transistors QA1, QA2 cause voltage drops of the virtual power supply lines VA1, VA2 from an LVDD value to (LVDDxe2x88x92xcex94VA1), (LVDDxe2x88x92xcex94VA2), respectively. Additionally, at this time, the voltage drop of the virtual power supply line VA1 is remarkably greater than that of the backgate power supply line VA2, establishing the relationship of xcex94VA1 greater than  greater than xcex94VA2. This is because the leakage current caused from the backgate power supply line VA2 to the transistors Q3, Q4 via the backgate is negligibly smaller than the active current from the virtual power supply line VA1 to the VB1 because of the operation of the internal circuit. The backgate potential is higher than that of each source of the transistors Q3, Q4, and the operations of the transistors Q3, Q4 are still made slower.
Therefore, it is an object of the present invention is to provide a semiconductor integrated circuit which achieves reduced power dissipation in the general circuit while suppressing a performance deterioration of an internal circuit in an active period. A semiconductor integrated circuit of the present invention comprises: a first field effect transistor including one source/drain electrode for receiving as a first power supply voltage, the other source/drain electrode connected to the first virtual power supply line, and a gate electrode for receiving a control signal so as to control ON/OFF of the transistor; a second field effect transistor, having one source/drain electrode connected to the first virtual power supply line and the other source/drain electrode connected to the first backgate power supply line, to be turned on when the first field effect transistor is turned on; and a third field effect transistor having one source/drain electrode connected to the first virtual power supply line and a backgate electrode connected to the first backgate power supply line, and which constructs an internal circuit. This causes a voltage drop to the first virtual power supply line on the first power supply line because of an ON-state resistance of the first field effect transistor and so on. Its forward bias state reduces the absolute value of the threshold voltage of the third field effect transistor by the voltage drop, thereby speeding up a current supply operation of the third field effect transistor. Therefore, an operation speed of the internal circuit constructed by the third field effect transistor may be improved.
When the third field effect transistor is p-channel type, the semiconductor integrated circuit further comprises: a fourth field effect transistor having one source/drain electrode for receiving a high power supply voltage, the other source/drain electrode connected to the first backgate power supply line, and a gate electrode for receiving a control signal so as to be turned on complimentarily with the first field effect transistor; and a potential generation circuit, connected to the first virtual power supply line, for generating a potential smaller than that of the first backgate power supply line on the first virtual power supply line when the first field effect transistor is turned off. In addition, the second field effect transistor has a gate electrode for receiving a control signal so as to be turned on complimentarily with the fourth field effect transistor. Thus, when the first field effect transistor is turned off, since the potential of the backgate electrode to one source/drain electrode of the third field effect transistor is enhanced, a leakage current of the third field effect transistor constructing the internal circuit is reduced, resulting in achieving a reduced power dissipation in the general circuit.
In this case, the backgate electrode of the first field effect transistor may be connected to the first backgate electrode line, and the backgate electrode of the second FET also connected to the first backgate electrode line.
Further, when the third field effect transistor is set to p-channel type, the semiconductor integrated circuit includes a common first power supply line, connected to one source/drain electrode of the first field effect transistor and one source/drain electrode of the fourth field effect transistor, in which the first voltage is supplied as the first and second power supply voltages when the first field effect transistor is turned on, and the second voltage having a voltage value higher than the first voltage is supplied as the first and second power supply voltages when the first field effect transistor is turned off. In this case, the backgate of the first, second, and fourth field effect transistors may be connected to the first backgate power supply line. However, supplies of the first and second voltages to the first power supply line may be performed by a voltage switching circuit.
On the other hand, the semiconductor integrated circuit comprises: a first high power supply line for supplying a first voltage as a high power supply voltage to one source/drain electrode of the first field effect transistor; and a second high power supply line for supplying a second voltage having a voltage value higher than that of the first voltage as the high power supply voltage to one source/drain electrode of the fourth field effect transistor. The first and second voltages are supplied to the first and fourth field effect transistors simultaneously. In this case, the backgate electrodes of the first and second field effect transistors may be connected to the first backgate electrode line.
When the third field effect transistor constructing the internal circuit is n-channel type, the semiconductor integrated circuit of the present invention comprises: a fourth field effect transistor having one source/drain electrode for receiving the low power supply voltage, the other source/drain electrode connected to the first backgate power supply line, and a gate electrode for receiving a control signal so as to be turned on complimentarily with the first field effect transistor; and a first potential generation circuit, connected to the first virtual power supply line, for generating a potential larger than that of the first backgate power supply line on the first virtual power supply line when the first field effect transistor is turned off. When the first field effect transistor is turned off, the potential of the backgate electrode to the one source/drain electrode of the third field effect transistor is lowered, thereby reducing a leakage current of the third field effect transistor constructing the internal circuit and achieving a reduced power dissipation of the general circuit. In this case, the backgate electrodes of the first, second and fourth transistors may be connected to the first backgate power supply line.
The semiconductor integrated circuit of the present invention comprises: a fifth field effect transistor having one source/drain electrode connected to a second power supply line, the other source/drain electrode connected to a second virtual power supply line, a gate electrode for receiving a control signal so as to control ON/OFF of the transistor, and a backgate electrode connected to said second power supply line; and a sixth field effect transistor, having one source/drain electrode connected to the second virtual power supply line and a backgate electrode connected to the second power supply line, which is different in conductance type from the third field effect transistor and which constructs an internal circuit of CMOS type with the third field effect transistor. In this case, when the semiconductor integrated circuit is formed on a semiconductor substrate of conductive type reverse to the sixth field effect transistor, it is not required to employ a so-called triple well structure in the substrate.
Here, the aforementioned semiconductor integrated circuit may comprise: a potential generation circuit, connected to the second virtual power supply line, for generating a potential difference between the power supply line and the second virtual power supply line when the fifth field effect transistor is turned off.
The potential generation circuit may include a construction such that one field effect transistor or a plurality of field effect transistors connected in series are connected between the first power supply line and the second virtual power supply line.
The potential generation circuit may include a construction such that one diode or a plurality of diodes connected in series are connected between the backgate power supply line and the first virtual power supply line.
The potential generation circuit may include a construction such that one field effect transistor or a plurality of field effect transistors connected in series are connected between the backgate power supply line and the first virtual power supply line, and the gate electrode and one source/drain electrode of each field effect transistor in the first potential generation circuit may be connected to each other.
The potential generation circuit may include a construction such that one diode or a plurality of diodes connected in series are connected between the first power supply line and the second virtual power supply line.
The potential generation circuit may include a construction such that one field effect transistor or a plurality of field effect transistors connected in series are connected between the first power supply line and the second virtual power supply line, and the gate electrode and one source/drain electrode of each field effect transistor in the potential generation circuit may be connected to each other.
The backgate electrodes of the first, second, and fourth field effect transistors may be connected to said first backgate power supply line.
Further, the semiconductor integrated circuit may comprise: a fourth field effect transistor having one source/drain electrode for receiving a second power supply voltage, the other source/drain electrode connected to the first backgate power supply line, and a gate electrode for receiving a control signal so as to be turned on complimentarily with the first field effect transistor; and a potential generating circuit connected to the first virtual power supply line, for generating a potential difference between the first backgate power supply line and said first virtual power supply line when the first field effect transistor is turned off, wherein the second field effect transistor has a gate electrode for receiving a control signal so as to be turned on complimentarily with the fourth field effect transistor.
Here, the first power supply voltage has a first voltage value when the first field effect transistor is turned on, and the second power supply voltage has a second voltage value different from the first voltage value when the first field effect transistor is turned off.
Furthermore, at least either of backgate electrodes of the first field effect transistor and the second field effect transistor may be connected to said first backgate power supply line.